ddr2 ddr3

Introduction

InthistutorialwewillexplorethemaintechnicaldifferencesbetweenDDR,

!

Beforewestartgoingintothespecifics,youneedtoknowthatDDR,DDR2

andDDR3arebasedonSDRAM(SynchronousDynamicRandomAccess

Memory)design,meaningthattheyuseaclocksignaltosynchronizethings.

DDRstandsforDoubleDataRate,meaningthatmemoriesfromthis

ation:theyachieve

doubletheperformanceofmemorieswithoutthisfeaturerunningatthe

sameclockrate(namelySDRAMmemories,whicharenotavailableforPCs

anymore).

Becauseofthisfeature,thesememoriesarelabeledwithdoublethereal

mple,DDR2-800memories

workat400MHz,DDR2-1066andDDR3-1066memoriesworkat533MHz,

DDR3-1333memorieswork666.6MHzandsoon.

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Figure1:ClocksignalandDDRmode.

Itisveryimportanttonoticethattheseclockratesarethemaximumthe

memorycanofficiallyuse;thisdoesnot,byanymean,thatthememorywill

workatthose“speeds”mple,ifyouinstallDDR2-1066

memoriesonacomputerthatcanonly(oritiswronglyconfiguredto)access

thememorysubsystemat400MHz(800MHzDDR),thememorieswillbe

accessedat400MHz(800MHzDDR)andnotat533MHz(1,066MHzDDR).

Thishappensbecausetheclocksignalisprovidedbythememorycontroller,

acircuitthatislocatedoutsidethememory(inthenorthbridgechipfromthe

motherboardorembeddedinsidetheCPU,dependingonthesystem).

ThisnamingsystemDDRx-yyyy(wherexisthetechnologygenerationand

yyyyistheDDRclockrate)

memorymodules–thelittleprintedcircuitboardwherethememorychips

aresolderedto–useadifferentnamingsystem:PCx-zzzz,wherexisthe

technologygenerationandzzzzisthemaximumtheoreticaltransferrate

(mbandwidth).Thisnumbergivesushowmanybytescanbe

transferredpersecondbetweenthememorycontrollerandthememory

moduleassumingthatdatawillbetransferredoneverysingleclockpulse.

willgiveusthemaximumtheoreticaltransferrateinMB/s(megabytesper

second).Forexample,DDR2-800memorieshaveamaximumtheoretical

transferrateof6,400MB/s(800x8)andmemorymodulesusingthiskindof

example,DDR3-1333memorieshaveamaximumtheoreticaltransferrate

of10,666MB/sbutmemorymodulesusingthiskindofmemoryarecalled

PC3-10666orPC3-10600,dependingonthemanufacturer.

Itisreallyimportanttounderstandthatthesenumbersaremaximum

ppensbecausefor

themathweareassumingthatthememorywillbesendingdatatothe

memorycontrollereverysingleclockcycle,whichsimplydoesn’thappen.

Thememorycontrollerandthememoryneedtoexchangecommands(for

example,acommandinstructingthememorytodeliverdatastoredata

givenposition)andduringsuchtimethememorywon’tbetransferringdata.

NowthatyouknowthebasicsaboutDDRmemories,let’stalkaboutthe

specifics.

Speeds

OneofthemaindifferencesbetweenDDR,DDR2andDDR3isthehighest

elistthemostcommonspeeds

nufacturerscandelivermemorychipscapable

ofachievingotherspeedsthanthoselisted–forexample,specialty

endingis33and66MHzarein

factperiodicdecimalexpansions(33.3333and66.6666,respectively).

MemoryRealMaximumTheoreticalTransferMemory

ClockRateModule

DDR200100MHz1,600MB/sPC-1600

DDR266133MHz2,133MB/sPC-2100

DDR333166MHz2,666MB/sPC-2700

DDR400200MHz3,200MB/sPC-3200

DDR2-400200MHz3,200MB/sPC2-3200

DDR2-533266MHz4,266MB/sPC2-4200

DDR2-667333MHz5,333MB/sPC2-5300

DDR2-800400MHz6,400MB/sPC2-6400

DDR2-1066533MHz8,533MB/sPC2-8500

DDR3-800400MHz6,400MB/sPC3-6400

DDR3-1066533MHz8,500MB/sPC3-8500

DDR3-1333666MHz10,666MB/sPC3-10600

DDR3-1600800MHz12,800MB/sPC3-12800

Voltages

DDR3memoriesoperateatlowervoltagescomparedtoDDR2memories,

meansthatDDR3memoriesconsumelesspowerthanDDR2memories,

whichinturnconsumelesspowerthanDDRmemories.

TypicallyDDRmemoriesarefedwith2.5V,DDR2memoriesarefedwith1.8

VandDDR3memoriesarefedwith1.5V(althoughmodulesrequiring1.6V

or1.65Varecommonandchipsrequiringonly1.35Vmaybecomecommon

inthefuture).Somememorymodulesmayrequirehighervoltagesthan

ppensespeciallywithmemoriessupportingthe

operationatclockrateshigherthantheofficialones(estargeted

tooverclocking).

TechnologyTypicalVoltage

DDR2.5V

DDR21.8V

DDR31.5V

Latency

Latencyisthetimethememorycontrollermustwaitbetweenrequestinga

soknownasCAS(Column

AddressStrobe)mberisexpressedintermsof

mple,amemorywithCL3meansthatthememory

controllermustwaitthreeclockcyclesuntildataisdeliveredafterarequest

emorywithCL5thememorycontrollerwillhavetowait

more:lwaysshouldlookforthememorymodules

withthelowestlatencypossible.

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Figure2:Latency.

DDR3memorieshavehigherlatenciesthanDDR2memories,whichinturn

2andDDR3memorieshave

anadditionalparametercalledAL(AdditionalLatency)

DDR2andDDR3memoriesthetotallatencywillbeCL+yenough

almostallDDR2andDDR3memoriesareAL0,meaningthatnoadditional

esummarizethemostcommonlatencyvalues.

TechnologyTypicalLatencyOtherCommonLatenciesAvailable

DDR32,2.5

DDR253,4

DDR376,8,9

ThismeansthatDDR3memoriesdelaymoreclockcyclestostartdelivering

datacomparedtoDDR2memories(justlikeDDR2memoriesdelaymore

clockcyclestostartdeliveringdatacomparedtoDDRmemories),butthis

notnecessarilymeansahigherwaittime(thiswillbetrueonlywhen

comparingmemoriesworkingattheexactsameclockrate).

Forexample,aDDR2-800CL5memorywilldelaylesstime(er)to

r,sincebothare

“800MHz”memories,bothprovidetheexactsamemaximumtheoretical

transferrate(6,400MB/s).AlsoitisimportanttorememberthattheDDR3

memorywillconsumelesspowerthantheDDR2one.

Whencomparingmoduleswithdifferentclockratesyouneedtososome

entionthatwearetalking

about“clockcycles”.Whentheclockishigher,eachclockcycleisshorter

(eriod).Forexample,onaDDR2-800memory,eachclockcycle

takes2.5ns(1ns=0.000,000,001second)–themathissimple,period=

1/frequency(notethatyouneedtousetherealclock,nottheDDRclockon

thisformula;tomakethingseasierwecompiledareferencetablebelow).So

supposingaDDR2-800memorywithCL5,thisinitialwaittimecorresponds

to12.5ns(2.5nsx5).

thismemoryeachclockcyclewillhaveaperiodof1.5ns(seetablebelow),

sothetotalwaittime(latency)willbeof10.5ns(1.5nsx7).Soeventhough

thelatencyofthisDDR3memoryappearstobehigher(7vs.5),thewait

’tgoaroundthinkingthatDDR3memorieshave

worselatenciesthanDDR2memories:itwilldependontheclockrateyou

aretalkingabout.

DDRClockRealClockClockPeriod

200MHz100MHz10ns

266MHz133MHz7.5ns

333MHz166MHz6ns

400MHz200MHz5ns

533MHz266MHz3.75ns

666MHz333MHz3ns

800MHz400MHz2.5ns

1,066MHz533MHz1.875ns

1,333MHz666MHz1.5ns

1,600MHz800MHz1.25ns

Usuallymanufacturersannouncethememorytimingsasaseriesofseveral

numbersseparatedbyadash(e.g.5-5-5-5,7-10-10-10,etc).TheCAS

exampleson

anttoknowwhattheothernumbersmean,please

readourtutorialUnderstandingRAMTimings.

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Figure3:DDR2-1066withCL5.

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Figure4:DDR3-1066withCL7.

Prefetch

memoriestransfertwobitsofdataperclockcyclefromthememoryarrayto

thememoryinternalI/2this

internaldatapathwasincreasedtofourbitsandonDDR3itwasraisedagain

actuallythetrickthatallowsDDR3toworkathigher

clockratesthanDDR2,andDDR2athigherclockratesthanDDR.

Theclockswewerereferringsofararetheclockratesonthe“external

world”,/Ointerfacefromthememory,wherethecommunication

ally,

however,thememoryworksalittlebitdifferently.

Tobetterunderstandthisidea,let’scompareaDDR-400,aDDR2-400anda

DDR3-400memorychip(weknowthatDDR3-400memoriesdon’texist,but

pretendtheydo).Thesethreechipsworkexternallyat200MHztransferring

twodataperclockcycle,achievinganexternalperformanceasiftheywere

ally,however,theDDRchiptransferstwobits

betweenthememoryarrayandtheI/Obuffer,sotomatchtheI/Ointerface

speedthisdatapathhastoworkat200MHz(200MHzx2=400MHz).Since

onDDR2thisdatapathwasincreasedfromtwobitstofourbits,itcanwork

athalftheclockrateinordertoachievethesameperformance(100MHzx

4=400MHz).WithDDR3thesamethinghappens:thedatapathwas

doubledagaintoeightbits,soitcanworkathalftheclockrateasDDR2or

only¼oftheclockrateofDDRinordertoachievethesameperformance

(50MHzx8=400MHz).

clicktoenlarge

Figure5:Understandingn-bitprefetching.

Doublingtheinternaldatapathateachgenerationmeansthateachnew

memorygenerationcanpredictablyhavechipmodelswithdoublethe

mple,on

DDR-400,DDR2-800andDDR3-1600memoriesthememoryworks

internallyatthesameclockrate(200MHz).

ResistiveTermination

OnDDRmemoriesthenecessaryresistiveterminationislocatedonthe

motherboard,whileonDDR2andDDR3memoriesthisterminationislocated

insidethememorychips–techniquecalledODT,On-DieTermination.

Thisisdoneinordertomakethesignals“cleaner”.InFigure5,youcansee

efthandsideyouseethe

signalsonasystemthatusesmotherboardtermination(DDRmemories)

whileontherighthandsideyouseethesignalsonasystemthatuseson-die

termination(DDR2andDDR3memories).Evenalaymancaneasilysaythat

thesignalsontherighthandsidearecleanerandstablethanthesignalson

ellowsquareyoucancomparethetimeframe

difference–thistimeframeisthetimethememoryhastoreadorwritea

euseofon-dieterminationthistimeframegotwider,

allowinghigherclockstobeachievedsincethememoryhasmoretimeto

readorwriteadatachunk.

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Figure6:Comparisonbetweenmotherboardterminationandon-die

termination.

PhysicalAspect

memorychips

alreadysolderedonaprintedcircuitboardcalled“memorymodule”.Memory

modulesforeachDDRgenerationarephysicallydifferentandyouwon’tbe

abletoinstallaDDR2moduleonaDDR3socket,your

motherboardsupportsbothDDR2andDDR3sockets(onlyafewdo)you

cannotupgradefromDDR2toDDR3withoutreplacingthemotherboardand

eventuallytheCPU(ifinyoursystemthememorycontrollerisembeddedin

theCPU,likeithappenswithallprocessorsfromAMDandCorei7from

Intel).ThesamethingisvalidwithDDRandDDR2:unlessforafewarerare

exceptions,2andDDR3

moduleshavethesamenumberofpins,howeverthekeynotchisplacedon

adifferentposition.

MemoryModuleNumberofPins

DDR184

DDR2240

DDR3240

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Figure7:DifferenceinedgecontactsbetweenDDRandDDR2.

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Figure8:DifferenceinedgecontactsbetweenDDR2andDDR3.

AllDDR2andDDR3chipsuseBGA(BallGridArray)packaging,whileDDR

chipsalmostalwaysuseTSOP(ThinSmall-OutlinePackage)packaging.

ThereareafewDDRchipswithBGApackagingonthemarket(liketheones

fromKingmax),re9,youcanseehowa

TSOPchiponaDDRmodulelookslikewhileinFigure10youcanseehowa

BGAchiponaDDR2lookslike.

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Figure9:DDRchipsalmostalwaysuseTSOPpackaging.

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Figure10:DDR2andDDR3chipsuseBGApackaging.